HD64F3670 Datasheet, PDF (10/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

3.4 Interrupt Exception Handling ....................................................................................... 48
3.4.1 External Interrupts........................................................................................... 48
3.4.2 Internal Interrupts............................................................................................ 49
3.4.3 Interrupt Handling Sequence............................................................................ 49
3.4.4 Interrupt Response Time.................................................................................. 51
3.5 Usage Notes................................................................................................................. 53
3.5.1 Interrupts after Reset ....................................................................................... 53
3.5.2 Notes on Stack Area Use ................................................................................. 53
3.5.3 Notes on Rewriting Port Mode Registers.......................................................... 53
Section 4 Address Break................................................................................ 55
4.1 Register Descriptions ................................................................................................... 55
4.1.1 Address Break Control Register (ABRKCR).................................................... 56
4.1.2 Address Break Status Register (ABRKSR)....................................................... 57
4.1.3 Break Address Registers (BARH, BARL)........................................................ 57
4.1.4 Break Data Registers (BDRH, BDRL) ............................................................. 57
4.2 Operation..................................................................................................................... 58
4.3 Usage Notes................................................................................................................. 59
Section 5 Clock Pulse Generators .................................................................. 61
5.1 System Clock Generator............................................................................................... 61
5.1.1 Connecting Crystal Resonator.......................................................................... 62
5.1.2 Connecting Ceramic Resonator........................................................................ 62
5.1.3 External Clock Input Method........................................................................... 63
5.2 Prescalers .................................................................................................................... 63
5.2.1 Prescaler S ...................................................................................................... 63
5.3 Usage Notes................................................................................................................. 63
5.3.1 Note on Resonators.......................................................................................... 63
5.3.2 Notes on Board Design.................................................................................... 64
Section 6 Power-Down Modes....................................................................... 65
6.1 Register Descriptions ................................................................................................... 66
6.1.1 System Control Register 1 (SYSCR1).............................................................. 66
6.1.2 System Control Register 2 (SYSCR2).............................................................. 68
6.1.3 Module Standby Control Register 1 (MSTCR1) ............................................... 69
6.2 Mode Transitions and States of LSI.............................................................................. 70
6.2.1 Sleep Mode ..................................................................................................... 72
6.2.2 Standby Mode ................................................................................................. 72
6.2.3 Subsleep Mode ................................................................................................ 72
6.3 Operating Frequency in Active Mode ........................................................................... 73
6.4 Direct Transition.......................................................................................................... 73
6.5 Module Standby Function ............................................................................................ 73
Rev. 2.0, 03/02, page viii of xxii