HD64F3670 Datasheet, PDF (57/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

2.6.2 On-Chip Peripheral Modules
On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits
or 16 bits depending on the register. For description on the data bus width and number of
accessing states of each register, refer to section 16.1, Register Addresses. Registers with 16-bit
data bus width can be accessed by word size only. Registers with 8-bit data bus width can be
accessed by byte or word size. When a register with 8-bit data bus width is accessed by word size,
access is completed in two cycles. In two-state access, the operation timing is the same as that for
on-chip memory.
Figure 2.10 shows the operation timing in the case of three-state access to an on-chip peripheral
module.
ø or ø_SUB
T₁ state
Bus cycle
T₂ state
T₃ state
Internal
address bus
Internal
read signal
Internal
data bus
(read access)
Internal
write signal
Internal
data bus
(write access)
Address
Read data
Write data
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)
Rev. 2.0, 03/02, page 33 of 298