HD64F3670 Datasheet, PDF (312/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Item
1.4 Pin Functions
Table 1.1 Pin Functions
Page
6
Revisions (See Manual for Details)
E10T E10T_0, 41, 42, 43 31, 32, 33 Interface pin for E10T
E10T_1,
emulator
E10T_2
2.1 Address Space and 8
Memory Map
Figure 2.1 Memory Map
HD64F3672
H'3FFF
H'4000
H'4FFF
E10T control
program area
(4 kbytes)
HD64F3670
H'4000
H'4FFF
E10T control
program area
(4 kbytes)
Rev.
2.0
2.0
4.1.1 Address Break
56
Control Register
(ABRKCR)
4.2 Operation
58
4.2 Operation
59
Figure 4.2 Address Break
Interrupt Operation
Example (3)
4.3 Usage Notes
59
H'F780
(1-kbyte work area
for flash memory
programming&E10T)
H'F780
(1-kbyte work area
for flash memory
programming&E10T)
H'FB7F
2.0
Bit Bit Name Description
4
ACMP2
Address Compare Condition Select 2 to 0
3
ACMP1
2
ACMP0
These bits comparison condition between
the address set in BAR and the internal
address bus.
000: Compares 16-bit addresses
001: Compares upper 12-bit addresses
010: Compares upper 8-bit addresses
011: Compares upper 4-bit addresses
1XX: Reserved (setting prohibited)
Description amended.
2.0
When the ABIF and ABIE bits in ABRKSR are set to
1, the address break function generates an interrupt
request to the CPU. The ABIF bit in ABRKSR is set to
1 by the combination of the address set in BAR, the
data set in BDR, and the conditions set in ABRKCR.
Deleted.
2.0
Added.
2.0
Rev. 2.0, 03/02, page 288 of 298