HD64F3670 Datasheet, PDF (19/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Figure 11.11 Buffer Operation Example (Output Compare)....................................................141
Figure 11.12 PWM Mode Example
(TOB, TOC, and TOD = 0: initial output values are set to 0) ...............................142
Figure 11.13 PWM Mode Example
(TOB, TOC, and TOD = 1: initial output values are set to 1) ...............................143
Figure 11.14 Count Timing for Internal Clock Source ............................................................144
Figure 11.15 Count Timing for External Clock Source ...........................................................144
Figure 11.16 Output Compare Output Timing ........................................................................145
Figure 11.17 Input Capture Input Signal Timing ....................................................................145
Figure 11.18 Timing of Counter Clearing by Compare Match ................................................146
Figure 11.19 Buffer Operation Timing (Compare Match) .......................................................146
Figure 11.20 Buffer Operation Timing (Input Capture)...........................................................147
Figure 11.21 Timing of IMFA to IMFD Flag Setting at Compare Match.................................147
Figure 11.22 Timing of IMFA to IMFD Flag Setting at Input Capture ....................................148
Figure 11.23 Timing of Status Flag Clearing by CPU .............................................................148
Figure 11.24 Contention between TCNT Write and Clear.......................................................149
Figure 11.25 Internal Clock Switching and TCNT Operation..................................................150
Section 12 Watchdog Timer
Figure 12.1 Block Diagram of Watchdog Timer .....................................................................151
Figure 12.2 Watchdog Timer Operation Example...................................................................154
Section 13 Serial Communication Interface3 (SCI3)
Figure 13.1 Block Diagram of SCI3 .......................................................................................156
Figure 13.2 Data Format in Asynchronous Communication....................................................169
Figure 13.3 Relationship between Output Clock and Transfer Data Phase
(Asynchronous Mode)(Example with 8-Bit Data, Parity, Two Stop Bits) ...............169
Figure 13.4 Sample SCI3 Initialization Flowchart ..................................................................170
Figure 13.5 Example SCI3 Operation in Transmission in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit) .........................................................................171
Figure 13.6 Sample Serial Transmission Flowchart (Asynchronous Mode) .............................172
Figure 13.7 Example SCI3 Operation in Reception in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit) .........................................................................173
Figure 13.8 Sample Serial Data Reception Flowchart (Asynchronous mode)(1) ......................175
Figure 13.8 Sample Serial Reception Data Flowchart (2)........................................................176
Figure 13.9 Data Format in Clocked Synchronous Communication ........................................177
Figure 13.10 Example of SCI3 Operation in Transmission in Clocked Synchronous Mode......178
Figure 13.11 Sample Serial Transmission Flowchart (Clocked Synchronous Mode)................179
Figure 13.12 Example of SCI3 Reception Operation in Clocked Synchronous Mode...............180
Figure 13.13 Sample Serial Reception Flowchart (Clocked Synchronous Mode).....................181
Figure 13.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
(Clocked Synchronous Mode).............................................................................183
Figure 13.15 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A)..........................................185
Rev. 2.0, 03/02, page xvii of xxii