HD64F3670 Datasheet, PDF (211/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

13.6.2 Multiprocessor Serial Data Reception
Figure 13.17 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in
SCR3 is set to 1, data is skipped until data with a 1 multiprocessor bit is received. On receiving
data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request
is generated at this time. All other SCI3 operations are the same as in asynchronous mode. Figure
13.18 shows an example of SCI3 operation for multiprocessor format reception.
Rev. 2.0, 03/02, page 187 of 298