HD64F3670 Datasheet, PDF (66/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

3.1 Exception Sources and Vector Address
Table 3.1 shows the vector addresses and priority of each exception handling. When more than
one interrupt is requested, handling is performed from the interrupt with the highest priority.
Table 3.1 Exception Sources and Vector Address
Relative Module Exception Sources
Vector
Number Vector Address
5(6 pin
Reset
0
H'0000 to H'0001
Watchdog timer

Reserved for system use
1 to 6 H'0002 to H'000D
External interrupt NMI
pin
7
H'000E to H'000F
CPU
Trap instruction (#0)
8
H'0010 to H'0011
(#1)
9
H'0012 to H'0013
(#2)
10
H'0014 to H'0015
(#3)
11
H'0016 to H'0017
Address break Break conditions satisfied
12
H'0018 to H'0019
CPU
Direct transition by executing the 13
SLEEP instruction
H'001A to H'001B
External interrupt IRQ0
pin
IRQ3
14
H'001C to H'001D
17
H'0022 to H'0023
WKP
18
H'0024 to H'0025

Reserved for system use
20
H'0028 to H'0029
Timer W
Input capture A/compare match A 21
H'002A to H'002B
Input capture B/compare match B
Input capture C/compare match C
Input capture D/compare match D
Timer W overflow
Timer V
Timer V compare match A
22
H'002C to H'002D
Timer V compare match B
Timer V overflow
SCI3
SCI3 receive data full
23
H'002E to H'002F
SCI3 transmit data empty
SCI3 transmit end
SCI3 receive error
A/D converter A/D conversion end
25
H'0032 to H'0033
Priority
High
Low
Rev. 2.0, 03/02, page 42 of 298