HD64F3670 Datasheet, PDF (84/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

When another interrupt request is accepted before an instruction to which an address break is set is
executed, exception handling of an address break interrupt is not executed. However, the ABIF bit
is set to 1 (see figure 4.4). Therefore the ABIF bit must be read during exception handling of an
address break interrupt.
[Register setting]
ABRKCR=H'80
BAR=H'0144
External interrupt
[Program]
001C 0900
:
:
0142 MOV.B #H'23,R1H
* ⁰¹⁴⁴ MOV.B #H'45,R1H
0146 MOV.B #H'67,R1H
Underlined indicates the addoress to be stacked.
MOV MOV MOV
instruction instruction instruction Internal
prefetch prefetch prefetch processing
Stack save
Vector ^{Internal External interrupt}
fetch ^{processing acceptance}
Adress bus
0142 0144
0146
SP-2 SP-4
001C
0900
Adress break
interrupt request
ABIF
External interrupt acceptance
Figure 4.4 Operation when Another Interrupt is Accepted at Address Break Setting
Instruction
Rev. 2.0, 03/02, page 60 of 298