HD64F3670 Datasheet, PDF (59/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Reset state
Reset cleared
Reset occurs
Exception-handling state
Reset
occurs
Reset
occurs
Interrupt
source
Interrupt
source
Exception-
handling
complete
Program halt state
Program execution state
SLEEP instruction executed
Figure 2.12 State Transitions
2.8 Usage Notes
2.8.1 Notes on Data Access to Empty Areas
The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip
I/O registers areas available to the user. When data is transferred from CPU to empty areas, the
transferred data will be lost. This action may also cause the CPU to malfunction. When data is
transferred from an empty area to CPU, the contents of the data cannot be guaranteed.
2.8.2 EEPMOV Instruction
EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4L,
which starts from the address indicated by R5, to the address indicated by R6. Set R4L and R6 so
that the end address of the destination address (value of R6 + R4L) does not exceed H'FFFF (the
value of R6 must not change from H'FFFF to H'0000 during execution).
2.8.3 Bit Manipulation Instruction
The BSET, BCLR, BNOT, BST, and BIST instructions read data from the specified address in
byte units, manipulate the data of the target bit, and write data to the same address again in byte
units. Special care is required when using these instructions in cases where two registers are
assigned to the same address or when a bit is directly manipulated for a port, because this may
rewrite data of a bit other than the bit to be manipulated.
Bit manipulation for two registers assigned to the same address
Example: Bit manipulation for the timer load register and timer counter
(Applicable for timer B and timer C, not for the series of this LSI.)
Rev. 2.0, 03/02, page 35 of 298