HD64F3670 Datasheet, PDF (183/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

13.3.5 Serial Mode Register (SMR)
SMR is used to set the SCI3’s serial transfer format and select the on-chip baud rate generator
clock source.
Bit Bit Name
7 COM
6 CHR
5 PE
4 PM
3 STOP
2 MP
Initial Value R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Description
Communication Mode
0: Asynchronous mode
1: Clocked synchronous mode
Character Length (enabled only in asynchronous
mode)
0: Selects 8 bits as the data length.
1: Selects 7 bits as the data length.
Parity Enable (enabled only in asynchronous
mode)
When this bit is set to 1, the parity bit is added to
transmit data before transmission, and the parity
bit is checked in reception.
Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.
Stop Bit Length (enabled only in asynchronous
mode)
Selects the stop bit length in transmission.
0: 1 stop bit
1: 2 stop bits
For reception, only the first stop bit is checked,
regardless of the value in the bit. If the second
stop bit is 0, it is treated as the start bit of the next
transmit character.
Multiprocessor Mode
When this bit is set to 1, the multiprocessor
communication function is enabled. The PE bit
and PM bit settings are invalid. In clocked
synchronous mode, this bit should be cleared to 0.
Rev. 2.0, 03/02, page 159 of 298