HD64F3670 Datasheet, PDF (186/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

13.3.7 Serial Status Register (SSR)
SSR is a register containing status flags of the SCI3 and multiprocessor bits for transfer. 1 cannot
be written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared.
Bit Bit Name
7 TDRE
Initial Value R/W
1
R/W
Description
Transmit Data Register Empty
Displays whether TDR contains transmit data.
[Setting conditions]
• When the TE bit in SCR3 is 0
• When data is transferred from TDR to TSR
6 RDRF
0
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE
=1
• When the transmit data is written to TDR
R/W Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
• When serial reception ends normally and
receive data is transferred from RSR to RDR
5 OER
0
[Clearing conditions]
• When 0 is written to RDRF after reading RDRF
=1
• When data is read from RDR
R/W Overrun Error
[Setting condition]
• When an overrun error occurs in reception
[Clearing condition]
• When 0 is written to OER after reading OER =
1
Rev. 2.0, 03/02, page 162 of 298