HD64F3670 Datasheet, PDF (141/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

OS3 and OS2 select the output level for compare match B. OS1 and OS0 select the output level
for compare match A. The two output levels can be controlled independently. After a reset, the
timer output is 0 until the first compare match.
10.3.5 Timer Control Register V1 (TCRV1)
TCRV1 selects the edge at the TRGV pin, enables TRGV input, and selects the clock input to
TCNTV.
Bit Bit Name Initial Value R/W
7 to 5 
All 1

4 TVEG1 0
R/W
3 TVEG0 0
R/W
2
TRGE
0
R/W
1

1

0 ICKS0 0
R/W
Description
Reserved
These bits are always read as 1.
TRGV Input Edge Select
These bits select the TRGV input edge.
00: TRGV trigger input is prohibited
01: Rising edge is selected
10: Falling edge is selected
11: Rising and falling edges are both selected
TCNTV starts counting up by the input of the edge which
is selected by TVEG1 and TVEG0.
0: Disables starting counting-up TCNTV by the input of
the TRGV pin and halting counting-up TCNTV when
TCNTV is cleared by a compare match.
1: Enables starting counting-up TCNTV by the input of
the TRGV pin and halting counting-up TCNTV when
TCNTV is cleared by a compare match.
Reserved
This bit is always read as 1.
Internal Clock Select 0
This bit selects clock signals to input to TCNTV in
combination with CKS2 to CKS0 in TCRV0.
Refer to table 10.2.
Rev. 2.0, 03/02, page 117 of 298