HD64F7047F50 Datasheet, PDF (83/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Instruction
Instruction Code
Operation
Execution
States T Bit
STS.L PR,@–Rn
0100nnnn00100010 Rn – 4 → Rn, PR → (Rn)
1

TRAPA #imm
11000011iiiiiiii PC/SR → stack area, (imm × 4 8

+ VBR) → PC
Note: * The number of execution states before the chip enters sleep mode:
The execution states shown in the table are minimums. The actual number of states
may be increased when (1) contention occurs between instruction fetches and data
access, or (2) when the destination register of the load instruction (memory → register)
equals to the register used by the next instruction.
Rev. 2.00, 09/04, page 41 of 720