HD64F7047F50 Datasheet, PDF (540/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

TPDR
When writing to free
operation address
2Td
Compare output
waveform
Dead time generation
waveform
Output generation
waveform
PWM waveform
Figure 16.5 Example of PWM Waveform Generation
0% to 100% Duty Cycle Output: In the operating modes, PWM waveforms with any duty cycle
from 0% to 100% can be output. The output PWM duty cycle is set using the buffer registers
(TBRU to TBRW).
100% duty cycle output is performed when the buffer register (TBRU to TBRW) value is set to
H'0000. The waveform in this case has positive phase in the 100% on state. 0% duty cycle output
is performed when a value greater than the TPDR value is set as the buffer register (TBRU to
TBRW) value. The waveform in this case has positive phase in the 100% off state.
External Counter Clear Function: In the operating modes, the TCNT counter can be cleared
from an external source. When using the counter clearing function, port A I/O register L
(PAIORL) should be used to set the PCIO pin as an input.
On the falling edge of PCIO pin (when set to input), the TCNT counter is reset to 2Td (the initial
setting). It then counts up until it reaches the value in TPDR, then starts counting down. When the
count returns to 2Td, TCNT starts counting up again, and this sequence is repeated. Figure 16.6
shows the example for counter clearing.
Rev. 2.00, 09/04, page 498 of 720