HD64F7047F50 Datasheet, PDF (643/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

23.5 Usage Notes
23.5.1 Initialization
The debugger's internal buffers and processing states are initialized in the following cases:
1. In a power-on reset
2. In hardware standby mode
3. When AUDRST is driven low
4. When the AUDSRST bit in the SYSCR register is cleared to 0 (see section 24.2.2)
5. When the MSTP3 bit in the MSTCR2 register is set to 1 (see section 24.2.3)
23.5.2 Operation in Software Standby Mode
The debugger is not initialized in software standby mode. However, since this LSI's internal
operation halts in software standby mode:
1. When AUDMD is high (RAM monitor mode), Ready is not returned (Not Ready continues to
be returned).
However, when operating on an external input clock, the protocol continues.
2. When AUDMD is low (branch trace mode), operation stops. However, operation continues
when software standby is released.
23.5.3 Setting the PA15/CK/POE6/TRST/BACK pin
There is a debugging tool for generating the AUDCK signal from the CK signal. See the manual
of the debugging tool to set the pin function controller (PFC).
23.5.4 Pin States
1. HSTBY/module standby
AUDMD
Z
AUDCK
Z
AUDSYNC Z
AUDATA Z
2. AUDRST = low-level input
AUDMD
Input
AUDCK
AUDSYNC
AUDRST
(1) AUDMD = high: Input
(1) AUDMD = high: Input
Low-level input
(2) AUDMD = low: High-level Output
(2) AUDMD = low: High-level Output
Rev. 2.00, 09/04, page 601 of 720