HD64F7047F50 Datasheet, PDF (752/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Item
Page Revisions (See Manual for Details)
15.3.1 Master Control
Register (MCR)
416 Bit 5:
Amended.
417 Bit 1:
Amended.
418 Bit 0:
Note added.
15.3.2 General Status
Register (GSR)
419 Bit 3:
Clearing condition amended.
15.3.5 Interrupt Request 426
Register (IRR)
Bit 0:
Initial value 0 → 1
15.3.8 Transmit Wait
Registers (TXPR1,
TXPR0)
430, Description amended.
431
15.3.9 Transmit Wait
432,
Cancel Registers (TXCR1, 433
TXCR0)
Description amended.
15.3.10 Transmit
434, Description amended.
Acknowledge Registers 435
(TXACK1, TXACK0)
15.3.11 Abort
436, Description amended.
Acknowledge Registers 437
(ABACK1, ABACK0)
15.3.12 Receive Complete 438,
Registers (RXPR1,
439
RXPR0)
Description amended.
15.3.13 Remote Request 440,
Registers (RFPR1,
441
RFPR0)
Description amended.
15.3.14 Mailbox Interrupt 442,
Mask Registers (MBIMR1, 443
MBIMR0)
Description amended.
15.3.15 Unread Message 444,
Status Registers (UMSR1, 445
UMSR0)
Description amended.
15.3.16 Mailboxes (MB0 447
to MB31)
Register Address
Data Bus
Name
15 14 13 12 11 10 9 8 7 6 5 4 3
MBx[0] to H'100 +
[1]
N*32
0
STDID[10:0]
MBx[2] to H'102 +
[3]
N*32
EXTID[15:0]
MBx[4] to
[5]
H'104 +
N*32
CCM
0
NMC ATX DART
MBC[2:0]
0 TCT 0 0
Note: Shaded bits are reserved. The write value should always be 0. The read value is not guaranteed.
Rev. 2.00, 09/04, page 710 of 720