HD64F7047F50 Datasheet, PDF (528/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

16.3 Register Descriptions
The MMT has the following registers. For details on register addresses and the register states
during each processing, refer to appendix A, Internal I/O Register.
• Timer mode register (MMT_TMDR*)
• Timer control register (TCNR)
• Timer status register (MMT_TSR*)
• Timer counter (MMT_TCNT*)
• Timer buffer register U (TBRU)
• Timer buffer register V (TBRV)
• Timer buffer register W (TBRW)
• Timer general register UU (TGRUU)
• Timer general register VU (TGRVU)
• Timer general register WU (TGRWU)
• Timer general register U (TGRU)
• Timer general register V (TGRV)
• Timer general register W (TGRW)
• Timer general register UD (TGRUD)
• Timer general register VD (TGRVD)
• Timer general register WD (TGRWD)
• Timer dead time counter 0 (TDCNT0)
• Timer dead time counter 1 (TDCNT1)
• Timer dead time counter 2 (TDCNT2)
• Timer dead time counter 3 (TDCNT3)
• Timer dead time counter 4 (TDCNT4)
• Timer dead time counter 5 (TDCNT5)
• Timer dead time data register (MMT_TDDR*)
• Timer period buffer register (TPBR)
• Timer period data register (TPDR)
Note: * In this section, the names of these registers are further abbreviated to TMDR, TSR,
TCNT, and TDDR hereafter.
Rev. 2.00, 09/04, page 486 of 720