HD64F7047F50 Datasheet, PDF (465/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Initial
Bit Bit Name Value R/W Description
14
IRR14
0
R/W Timer Compare Match Interrupt Flag 0
Indicates that a compare match occurred in TCMR0.
0: Timer compare match has not occurred in TCMR0
1: Timer compare match has occurred in TCMR0
[Clearing condition]
• Writing 1
[Setting condition]
• TCMR0 = TCNTR
Note: This bit is not set when TCMR0 = H'0000.
13
IRR13
0
R/W Timer Overflow Interrupt Flag
Indicates that the timer has overflowed.
0: Timer has not overflowed
1: Timer has overflowed
[Clearing condition]
• Writing 1
[Setting condition]
• Timer has overflowed and the value of TCNTR
changes from H'FFFF to H'0000.
Note: This bit is set even when TCMR0 is enabled to clear the
timer value and its value is set to H'FFFF.
12
IRR12
0
R/W Bus Operation Interrupt Flag
Status flag indicating detection of a dominant bit due to
bus operation when the HCAN2 module is in HCAN2
sleep mode.
0: Bus idle state (during HCAN2 sleep mode)
1: CAN bus operation (during HCAN2 sleep mode)
[Clearing condition]
• Writing 1
[Setting condition]
• When the bus operation (dominant bit) is detected
during HCAN2 sleep mode
11, 10 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 2.00, 09/04, page 423 of 720