HD64F7047F50 Datasheet, PDF (444/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Pφ
CMCNT
input clock
CMCNT
N
0
CMCOR
N
Compare
match signal
CMF
CMI
Figure 14.4 CMF Set Timing
14.4.3 Compare Match Flag Clear Timing
The CMF bit of the CMCSR register is cleared by writing 0 to it after reading 1 or the clearing
signal after the DTC transfer. Figure 14.5 shows the timing when the CMF bit is cleared by the
CPU.
CMCSR write cycle
T1 T2
Pφ
CMF
Figure 14.5 Timing of CMF Clear by the CPU
Rev. 2.00, 09/04, page 402 of 720