HD64F7047F50 Datasheet, PDF (183/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

9.6 Accessing External Space
A strobe signal is output in external space accesses to provide primarily for SRAM or ROM direct
connections.
9.6.1 Basic Timing
External access bus cycles are performed in 2 states. Figure 9.3 shows the basic timing of external
space access.
CK
Address
CS0
Read
RD
Data
Write
WRL
Data
T1
T2
Figure 9.3 Basic Timing of External Space Access
During a read, irrespective of operand size, all bits (8 bits in this LSI) in the data bus width for the
access space (address) accessed by RD signal are fetched by the LSI.
During a write, the WRL (bits 7 to 0) signal indicates the byte location to be written.
Rev. 2.00, 09/04, page 141 of 720