HD64F7047F50 Datasheet, PDF (586/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

18.4.1 Register Descriptions
Port E has the following registers. For details on register addresses and register states during each
processing, refer to appendix A, Internal I/O Register.
• Port E data register H (PEDRH)
• Port E data register L (PEDRL)
18.4.2 Port E Data Registers H and L (PEDRH and PEDRL)
The port E data registers H and L (PEDRH and PEDRL) are 16-bit readable/writable registers that
store port E data. Bits PE21DR to PE0DR correspond to pins PE21 to PE0 (multiplexed functions
omitted here).
When a pin functions is a general output, if a value is written to PEDRH or PEDRL, that value is
output directly from the pin, and if PEDRH or PEDRL is read, the register value is returned
directly regardless of the pin state.
When a pin functions is a general input, if PEDRH or PEDRL is read, the pin state, not the register
value, is returned directly. If a value is written to PEDRH or PEDRL, although that value is
written into PEDRH or PEDRL it does not affect the pin state. Table 18.4 summarizes port E data
register read/write operations.
PEDRH:
Bit
Bit Name Initial Value R/W
15 to 6 —
All 0
R
5
PE21DR 0
R/W
4
PE20DR 0
R/W
3
PE19DR 0
R/W
2
PE18DR 0
R/W
1
PE17DR 0
R/W
0
PE16DR 0
R/W
Description
Reserved
These bits are always read as 0, and should only be
written with 0.
See table 18.4.
Rev. 2.00, 09/04, page 544 of 720