HD64F7047F50 Datasheet, PDF (571/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

17.1.3 Port B I/O Register (PBIOR)
The port B I/O register (PBIOR) is a 16-bit readable/writable register that is used to set the pins on
port B as inputs or outputs. Bits PB5IOR to PB0IOR correspond to pins PB5 to PB0 (names of
multiplexed pins are here given as port names and pin numbers alone). PBIOR is enabled when
port B pins are functioning as general-purpose inputs/outputs (PB5 to PB0) and SCK4 pins are
functioning as inputs/outputs of SCI. In other states, PBIOR is disabled.
A given pin on port B will be an output pin if the corresponding bit in PBIOR is set to 1, and an
input pin if the bit is cleared to 0.
Bits 15 to 6 are reserved. These bits are always read as 0 and should only be written with 0.
The initial vale of PBIOR is H'0000.
17.1.4 Port B Control Registers 1 and 2 (PBCR1 and PBCR2)
The port B control registers 1 and 2 (PBCR1 and PBCR2) are 16-bit readable/writable registers
that are used to select the multiplexed pin function of the pins on port B.
Port B Control Registers 1 and 2 (PBCR1 and PBCR2)
Register
PBCR1
PBCR1
PBCR2
PBCR1
PBCR2
PBCR2
Bit
15 to 14
8 to 0
15 to 12
13
11
10
Bit Name



PB5MD2
PB5MD1
PB5MD0
Initial
Value
All 0
All 0
All 0
0*¹
0
0*¹
R/W
R
R
R
R/W
R/W
R/W
PBCR1 12
PB4MD2 0
R/W
PBCR2 9
PB4MD1 0
R/W
PBCR2 8
PB4MD0 0
R/W
Description
Reserved
These bits are always read as 0 and should only be
written with 0.
PB5 Mode
Select the function of the PB5/IRQ3/POE3/CK pin.
000: PB5 I/O (port)
100: Setting prohibited
001: IRQ3 input (INTC) 101: CK output (CPG)
010: POE3 input (port) 110: Setting prohibited
011: Setting prohibited 111: Setting prohibited
PB4 Mode
Select the function of the PB4/IRQ2/POE2/SCK4 pin.
000: PB4 I/O (port)
100: Setting prohibited
001: IRQ2 input (INTC) 101: Setting prohibited
010: POE2 input (port) 110: Setting prohibited
011: Setting prohibited 111: SCK4 I/O (SCI)
Rev. 2.00, 09/04, page 529 of 720