HD64F7047F50 Datasheet, PDF (431/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

A/D conversion time (t_CONV)
A/D conversion start Analog input
delay time(tD) sampling time(tSPL)
Write cycle
A/D synchronization time
(Up to
(3 states) _{59 states)}
Pφ
Address
Internal write
signal
Analog input
sampling
signal
A/D converter
ADST write timing
Idle state
Sample-and-hold A/D conversion
ADF
End of A/D conversion
Figure 13.2 A/D Conversion Timing
Table 13.3 A/D Conversion Time (Single Mode)
CKS1 = 0
CKS0 = 0
CKS0 = 1
Item
Symbol Min Typ Max Min Typ Max
A/D conversion t_D
start delay time
31  62 15  30
Input sampling t
SPL
time
 256   128 
A/D conversion t
CONV
time
1024  1055 515  530
Note: All values represent the number of states for Pφ.
CKS1 = 1
CKS0 = 0
CKS0 = 1
Min Typ Max Min Typ Max
7  14 3  6
 64   32 
259  266 131  134
Rev. 2.00, 09/04, page 389 of 720