HD64F7047F50 Datasheet, PDF (382/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

12.3.8 Serial Direction Control Register (SDCR)
The DIR bit in the serial direction control register (SDCR) selects LSB-first or MSB-first transfer.
With an 8-bit data length, LSB-first/MSB-first selection is available regardless of the
communication mode. With a 7-bit data length, LSB-first transfer must be selected. The
description in this section assumes LSB-first transfer.
Bit
7 to 4
Bit Name

Initial
Value
All 1
3
DIR
0
2

0
1

1
0

0
R/W Description
R
Reserved
The write value must always be 1. Operation cannot
be guaranteed if 0 is written.
R/W Data Transfer Direction
Selects the serial/parallel conversion format. Valid for
an 8-bit transmit/receive format.
0: TDR contents are transmitted in LSB-first order
Receive data is stored in RDR in LSB-first
1: TDR contents are transmitted in MSB-first order
Receive data is stored in RDR in MSB-first
R
Reserved
The write value must always be 0. Operation cannot
be guaranteed if 1 is written.
R
Reserved
This bit is always read as 1, and cannot be modified.
R
Reserved
The write value must always be 0. Operation cannot
be guaranteed if 1 is written.
12.3.9 Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 12.2 shows
the relationships between the N setting in BRR and the effective bit rate B₀ for asynchronous and
clocked synchronous modes. The initial value of BRR is H'FF, and it can be read or written to by
the CPU at all times.
Rev. 2.00, 09/04, page 340 of 720