HD64F7047F50 Datasheet, PDF (568/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Port A Control Registers L3 to L1 (PACRL3 to PACRL1)
Register Bit
PACRL3 15
PACRL1 15
PACRL1 14
PACRL3 14
PACRL1 13
PACRL1 12
PACRL3 13
PACRL1 11
PACRL1 10
PACRL3 12
PACRL1 9
PACRL1 8
PACRL3 11
PACRL1 7
PACRL1 6
Initial
Bit Name Value R/W
PA15MD2 0*²
R/W
PA15MD1 0
R/W
PA15MD0 0
R/W
PA14MD2 0*²
R/W
PA15MD1 0
R/W
PA14MD0 0
R/W
PA13MD2 0*²
R/W
PA13MD1 0
R/W
PA13MD0 0
R/W
PA12MD2 0*²
R/W
PA12MD1 0
R/W
PA12MD0 0
R/W
PA11MD2 0
R/W
PA11MD1 0
R/W
PA11MD0 0
R/W
Description
PA15 Mode
Select the function of the PA15/CK/POE6/TRST/BACK
pin.
000: PA15 I/O (port)
100: TRST input (H-UDI)*¹
001: CK output (CPG)
101: BACK output (BSC)
010: POE6 input (port)
110: Setting prohibited
011: Setting prohibited
111: Setting prohibited
PA14 Mode
Select the function of the PA14/RD/POE5/TMS pin.
000: PA14 I/O (port)
100: TMS input (H-UDI)*¹
001: RD output (BSC)
101: Setting prohibited
010: POE5 input (port)
110: Setting prohibited
011: Setting prohibited
111: Setting prohibited
PA13 Mode
Select the function of the PA13/POE4/TDO/BREQ pin.
000: PA13 I/O (port)
100: TDO output(H-UDI)*¹
001: Setting prohibited
101: BREQ input (BSC)
010: POE4 input (port)
110: Setting prohibited
011: Setting prohibited
111: Setting prohibited
PA12 Mode
Select the function of the PA12/WRL/UBCTRG/TDI pin.
000: PA12 I/O (port)
100: TDI input (H-UDI)*¹
001: WRL output (BSC)
101: Setting prohibited
010: UBCTRG output (UBC)*¹ 110: Setting prohibited
011: Setting prohibited
111: Setting prohibited
PA11 Mode
Select the function of the PA11/ADTRG/SCK3 pin.
000: PA11 I/O (port)
100: Setting prohibited
001: Setting prohibited
010: ADTRG input (A/D)
101: SCK3 I/O (SCI)
110: Setting prohibited
011: Setting prohibited
111: Setting prohibited
Rev. 2.00, 09/04, page 526 of 720