HD64F7047F50 Datasheet, PDF (118/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

6.3.1 Interrupt Control Register 1 (ICR1)
ICR1 is a 16-bit register that sets the input signal detection mode of the external interrupt input
pins NMI and IRQ0 to IRQ3 and indicates the input signal level at the NMI pin.
Initial
Bit Bit Name Value
15
NMIL
1/0
14 to 9 
All 0
8
NMIE
0
7
IRQ0S
0
6
IRQ1S
0
R/W Description
R
NMI Input Level
Sets the level of the signal input to the NMI pin. This
bit can be read to determine the NMI pin level. This
bit cannot be modified.
0: NMI input level is low
1: NMI input level is high
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W NMI Edge Select
0: Interrupt request is detected on falling edge of NMI
input
1: Interrupt request is detected on rising edge of NMI
input
R/W IRQ0 Sense Select
This bit sets the IRQ0 interrupt request detection
mode.
0: Interrupt request is detected on low level of IRQ0
input
1: Interrupt request is detected on edge of IRQ0 input
(edge direction is selected by ICR2)
R/W IRQ1 Sense Select
This bit sets the IRQ1 interrupt request detection
mode.
0: Interrupt request is detected on low level of IRQ1
input
1: Interrupt request is detected on edge of IRQ1 input
(edge direction is selected by ICR2)
Rev. 2.00, 09/04, page 76 of 720