HD64F7047F50 Datasheet, PDF (189/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

This LSI
External device
BREQ accepted
Strobe pin:
high-level output
Address, data, strobe pin:
high impedance
Bus release response
BREQ = Low
BACK = Low
Bus request
BACK confirmation
Bus mastership release status
Bus mastership acquisition
Figure 9.8 Bus Mastership Release Procedure
9.9 Memory Connection Example
SH7047
CS0
RD
A0 to A14
D0 to D7
32 k × 8-bit ROM
CE
OE
A0 to A14
I/O0 to I/O7
Figure 9.9 Example of 8-bit Data Bus Width ROM Connection
Rev. 2.00, 09/04, page 147 of 720