HD64F7047F50 Datasheet, PDF (181/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

9.5.2 Bus Control Register 2 (BCR2)
BCR2 is a 16-bit readable/writable register that specifies the number of idle cycles and CS0 signal
assert extension of each CS0 space.
Bit
Bit Name
15 to 10 
Initial
Value
All 1
9
IW01
1
8
IW00
1
7 to 5 
All 1
4
CW0
1
3 to 1 
All 1
0
SW0
1
R/W Description
R
Reserved
These bits are always read as 1 and should always
be written with 1.
R/W Idle Specification between Cycles
R/W These bits insert idle cycles when a read access is
followed immediately by a write access.
00: No CS0 space idle cycle
01: One CS0 space idle cycle
10: Two CS0 space idle cycles
11: Three CS0 space idle cycles
R
Reserved
These bits are always read as 1 and should always
be written with 1.
R/W Idle Specification for Continuous Access
The continuous access idle specification makes
insertions to clearly delineate the bus intervals by
once negating the CS0 signal when performing
consecutive accesses to the same CS space.
0: No CS0 space continuous access idle cycles
1: One CS0 space continuous access idle cycle
When a write immediately follows a read, the number
of idle cycles inserted is the larger of the two values
specified by IWO1 and IWO0.
R
Reserved
These bits are always read as 1 and should always
be written with 1.
R/W CS Assert Extension Specification
The CS assert cycle extension specification is for
making insertions to prevent extension of the RD
signal or WRL signal assert period beyond the length
of the CS0 signal assert period.
0: No CS0 space CS assert extension
1: CS0 space CS assert extension (one cycle is
inserted before and after each bus cycle)
Rev. 2.00, 09/04, page 139 of 720