HD64F7047F50 Datasheet, PDF (519/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

15.5 Interrupt Sources
Table 15.6 lists the HCAN2 interrupt sources. With the exception of the reset processing interrupt
(IRR0) by a power-on reset, these sources can be masked. Masking is implemented using the
mailbox interrupt mask register (MBIMR) and interrupt mask register (IMR). For details on the
interrupt vector of each interrupt source, refer to section 6, Interrupt Controller (INTC).
Table 15.6 HCAN2 Interrupt Sources
Name
ERS1
OVR1
RM1
SLE1
Description
Error passive interrupt (TEC ≥ 128 or REC ≥ 128)
Bus off interrupt (TEC ≥ 256)/bus off recovery interrupt
Error warning interrupt (TEC ≥ 96)
Error warning interrupt (REC ≥ 96)
Reset processing interrupt by power-on reset
Overload frame transmission interrupt
Unread message overwrite/overrun
Detection of CAN bus operation in HCAN2 sleep mode
Timer overflow
Compare-match condition occurred in TCMR0
Compare-match condition occurred in TCMR1
Data frame reception
Remote frame reception
Mailbox empty
Interrupt
Flag
IRR5
IRR6
IRR3
IRR4
IRR0
IRR7
IRR9
IRR12
IRR13
IRR14
IRR15
IRR1
IRR2
IRR8
DTC
Activation
Not possible
Not possible
Possible
Not possible
Rev. 2.00, 09/04, page 477 of 720