HD64F7047F50 Datasheet, PDF (619/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 20 Mask ROM
This LSI is available with 128 kbytes of on-chip ROM. The on-chip ROM is connected to the
CPU and data transfer controller (DTC) through a 32-bit data bus (figures 20.1). The CPU and
DTC can access the on-chip ROM in 8, 16 and 32-bit widths. Data in the on-chip ROM can
always be accessed in one cycle.
Internal data bus (32 bits)
H'00000000
H'00000004
H'00000001
H'00000005
H'00000002
H'00000006
H'00000003
H'00000007
On-chip ROM
H'0001FFFC
H'0001FFFD
H'0001FFFE
H'0001FFFF
Figure 20.1 Mask ROM Block Diagram
The operating mode determines whether the on-chip ROM is valid or not. The operating mode is
selected using mode-setting pins FWP and MD3 to MD0 as shown in table 3.1. If you are using
the on-chip ROM, select mode 2 or mode 3; if you are not, select mode 0 or mode 1. The on-chip
ROM is allocated to addresses H'00000000 to H'0001FFFF.
20.1 Notes on Use
• Setting module standby mode
For mask ROM, this module can be disabled/enabled by the module standby control register.
Mask ROM operation is enabled for the initial value. Accessing mask ROM is disabled by
setting module standby mode. For more information, see section 24, Power-Down Modes.
Rev. 2.00, 09/04, page 577 of 720