HD64F7047F50 Datasheet, PDF (47/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

1.3 Pin Arrangement
PD8/UBCTRG 76
VCL 77
PD7/D7/AUDSYNC 78
PD6/D6/AUDCK 79
PD5/D5/AUDMD 80
PD4/D4/AUDRST 81
VSS 82
*²FWP 83
VCC 84
HSTBY 85
PD3/D3/AUDATA3 86
RES 87
PD2/D2/SCK2/AUDATA2 88
NMI 89
PD1/D1/TXD2/AUDATA1 90
MD3 91
PD0/D0/RXD2/AUDATA0 92
MD2 93
MD1 94
MD0 95
EXTAL 96
XTAL 97
PLLVCL 98
PLLCAP 99
PLLVSS 100
QFP-100
(Top view)
50 VSS
49 AVSS
48 PF0/AN0
47 PF8/AN8
46 AVCC
45 PF1/AN1
44 PF9/AN9
43 PF2/AN2
42 PF10/AN10
41 PF3/AN3
40 PF11/AN11
39 PF12/AN12
38 PF4/AN4
37 PF13/AN13
36 PF5/AN5
35 PF14/AN14
34 PF6/AN6
33 AVCC
32 PF15/AN15
31 PF7/AN7
30 AVSS
29 VSS
28 PE21/PWOB/SCK4/A15
27 VCL
26 PE20/PVOB/TXD4/A14
Notes: *1 Pin for E10A debugging mode
DBGMD: Fixed to Vcc for the MASK version. Used as the DBGMD input pin for the F-ZTAT version.
ASEBRKAK:
Product
Processing method
Vcc fixed Vcc fixed Pull up Pull down NC
MASK version
Enabled Enabled Enabled Enabled Enabled
F-ZTAT version (E10A used) Disabled Disabled Enabled Disabled Enabled
F-ZTAT version (E10A unused) Disabled Disabled Enabled Enabled Enabled
*2 For the mask ROM version, connect this pin to Vcc
Figure 1.2 SH7047 Pin Arrangement
Rev. 2.00, 09/04, page 5 of 720