HD64F7047F50 Datasheet, PDF (587/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

PEDRL:
Bit Bit Name Initial Value R/W
15 PE15DR 0
R/W
14 PE14DR 0
R/W
13 PE13DR 0
R/W
12 PE12DR 0
R/W
11 PE11DR 0
R/W
10 PE10DR 0
R/W
9
PE9DR
0
R/W
8
PE8DR
0
R/W
7
PE7DR
0
R/W
6
PE6DR
0
R/W
5
PE5DR
0
R/W
4
PE4DR
0
R/W
3
PE3DR
0
R/W
2
PE2DR
0
R/W
1
PE1DR
0
R/W
0
PE0DR
0
R/W
Description
See table 18.4.
Table 18.4 Port E Data Registers H and L (PEDRH and PEDRL) Read/Write Operations
Bits 5 to 0 in PEDRH and bits 15 to 0 in PEDRL:
PEIOR Pin Function Read
Write
0
General input Pin state
Can write to PEDRH or PEDRL, but it has no
effect on pin state
Other than
general input
Pin state
Can write to PEDRH or PEDRL, but it has no
effect on pin state
1
General output PEDRH or
Value written is output from pin (POE pin = high)*
PEDRL value _{High impedance regardless of PEDRH or PEDRL}
value (POE pin = low)*
Other than
PEDRH or
Can write to PEDRH or PEDRL, but it has no
general output PEDRL value effect on pin state
Note: * Control by the POE pin is only available for high current-output pins (PE9 and PE11 to
PE21).
Rev. 2.00, 09/04, page 545 of 720