HD64F7047F50 Datasheet, PDF (287/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

TGCR
UF bit
VF bit
WF bit
6-phase output TIOC3B pin
TIOC3D pin
TIOC4A pin
TIOC4C pin
TIOC4B pin
TIOC4D pin
When BDC = 1, N = 1, P = 1, FB = 1, output active level = high
Figure 10.53 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2)
14. A/D Conversion Start Request Setting
In complementary PWM mode, an A/D conversion start request can be set using a TGRA_3
compare-match or a compare-match on a channel other than channels 3 and 4.
When start requests using a TGRA_3 compare-match are set, A/D conversion can be started at
the center of the PWM pulse.
A/D conversion start requests can be set by setting the TTGE bit to 1 in the timer interrupt
enable register (TIER).
Rev. 2.00, 09/04, page 245 of 720