|
HD64F7047F50 Datasheet, PDF (301/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents | |||
|
◁ |
10.7.3 Caution on Period Setting
When counter clearing on compare match is set, TCNT is cleared in the final state in which it
matches the TGR value (the point at which the count value matched by TCNT is updated).
Consequently, the actual counter frequency is given by the following formula:
f = PÏ
(N + 1)
Where
f: Counter frequency
PÏ: Peripheral clock operating frequency
N: TGR set value
10.7.4 Contention between TCNT Write and Clear Operations
If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes
precedence and the TCNT write is not performed.
Figure 10.71 shows the timing in this case.
TCNT write cycle
T1 T2
PÏ
Address
TCNT address
Write signal
Counter clear
signal
TCNT
N
H'0000
Figure 10.71 Contention between TCNT Write and Clear Operations
Rev. 2.00, 09/04, page 259 of 720
|
▷ |