HD64F7047F50 Datasheet, PDF (644/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

AUDATA (1) AUDMD = high: Input
(2) AUDMD = low: High-level Output
3. Normal operation/software standby
AUDSRST = 1
AUDMD
Input
AUDCK
(1) AUDMD = high: Input
AUDSYNC (1) AUDMD = high: Input
(2) AUDMD = low: Output
(2) AUDMD = low: Output
AUDRST
High-level input
AUDATA (1) AUDMD = high: Input/Output (2) AUDMD = low: Output
23.5.5 AUD Activation Procedures
The following procedures should be followed.
1. Select the AUD as a pin function by specifying the PFC.
2. Input the clock signal to the AUDCK pin for three cycles at the minimum keeping the
AUDRST pin low.
3. Set the AUD reset bit (AUDSRST) in SYSCR to cancel the AUD reset.
Setting the AUDRST pin to the low level and inputting the clock signal to the AUDCK pin can be
done before selection of the AUD as a pin function.
Rev. 2.00, 09/04, page 602 of 720