HD64F7047F50 Datasheet, PDF (492/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Register
Name Bit
MBx[4], 11
MBx[5]
Bit Name
DART
10 to 8 MBC[2:0]
7

6
TCT
5, 4
—
R/W Description
R/W Disable Automatic Re-Transmission
When this bit is set to 1, it disables the automatic re-
transmission of a message in the event of an error
on the CAN bus or an arbitration lost on the CAN
bus, thereby failed to obtain bus mastership. In
effect, when this function is used, the corresponding
TXCR bit is automatically set at the start of
transmission. When this bit is cleared to 0, the
HCAN2 tries to transmit the message as many times
as required until it is successfully transmitted or it is
cancelled by TXCR.
Note:
This function is not supported in this LSI.
Therefore, the write value should always be
0. The read value is not guaranteed.
R/W Mailbox Configuration
Set mailboxes as shown in table 15.2.
R/W The initial value of this bit is undefined; it must be
initialized (by writing 0).
R/W Timer Counter Transfer
When this bit is set to 1, a mailbox is configured as a
transmit mailbox, and its DLC is set to 2 or 4 and
later, the TCNTR value at the SOF is included in the
two or three bytes of the message data, instead of
MSG_DATA_2 and MSG_DATA_3. Then value of
cycle counter is included in the first byte, instead of
MSG_DATA_0. This function will be useful when the
HCAN2 performs a time master role. Table 15.3 lists
details of configuration of message data area.
Note:
This function is not supported in this LSI.
Therefore, the write value should always be
0. The read value is not guaranteed.
R/W The initial value of these bits are undefined; they
must be initialized (by writing 0).
Rev. 2.00, 09/04, page 450 of 720