HD64F7047F50 Datasheet, PDF (178/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

9.4 Address Map
Figure 9.2 shows the address format used by this LSI.
A31 to A24
A23, A22
A21 to A18
A17
A0
Output address:
Output from the address pins
CS space selection:
Decoded, outputs CS0 when A31 to A24 = 00000000
Space selection:
Not output externally; used to select the type of space
On-chip ROM space or CS0 space when 00000000 (H'00)
Reserved (do not access) when 00000001 to 11111110 (H'01 to H'FE)
On-chip peripheral module space or on-chip RAM space when 11111111 (H'FF)
Figure 9.2 Address Format
This chip uses 32-bit addresses:
• Bits A31 to A24 are used to select the type of space and are not output externally.
• Bits A23 and A22 are decoded and output as chip select signals (CS0) for the corresponding
areas when bits A31 to A24 are 00000000.
• A17 to A0 are output externally. A21 to A18 are not output externally.
Table 9.2 shows the address map.
Rev. 2.00, 09/04, page 136 of 720