HD64F7047F50 Datasheet, PDF (747/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Main Revisions and Additions in this Edition
Item
Precaution on Handling
HCAN2
1.4 Pin Functions
Page
All
Revisions (See Manual for Details)
SH7047 Series → SH7047 group
Added.
10
Type
Symbol
Function
User break
UBCTRG
controller (UBC)
(flash memory
version only)
UBC condition match trigger output pin.
Figure 3.2 The Address 49
Map for the Operating
Modes of SH7049 Mask
ROM Version
4.3.1 Note on Crystal
55
Resonator
Table 5.3 Exception
60
Processing Vector Table
H'00000000
Mode 0
CS0 area
ROM: 128 kbytes, RAM: 8 kbytes
H'00000000
Mode 2
On-chip ROM
H'00000000
H'0001FFFF
Mode 3
On-chip ROM
H'FFFFDFFF
H'FFFFE000
Reserved area
On-chip RAM
H'FFFFDFFF
H'FFFFE000
Reserved area
On-chip RAM
H'FFFFE000
On-chip RAM
H'FFFFFFFF
H'FFFFFFFF
H'FFFFFFFF
As the resonator circuit constants will depend on the resonator
and the floating capacitance of the mounting circuit, the
component value should be determined in consultation with the
resonator manufacturer.
Exception Sources
Vector Numbers Vector Table Address Offset
On-chip peripheral module *² 72
:
255
H'00000120 to H'00000123
:
H'000003FC to H'000003FF
Table 9.2 Address Map 137 • On-chip ROM disabled mode
Address
Space*
H'0004 0000 to H'FFFF 7FFF
Reserved
Memory
Reserved
Table 10.10 TIORH_0 164 to Output hold* → Output hold
(channel 0) to Table 10.25 179
TIORL_4 (channel 4)
Table 10.24 TIORL_4
(channel 4)
178
Notes: 2. When the BFB bit in TMDR_4 is set to 1 and TGRC_4 is used as a
buffer register, this setting is invalid and input capture/output compare
is not generated.
Rev. 2.00, 09/04, page 705 of 720