HD64F7047F50 Datasheet, PDF (499/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Initial
Bit Bit Name Value R/W Description
5
TPSC5
0
R/W HCAN2 Timer Prescaler
4
TPSC4
0
3
TPSC3
0
2
TPSC2
0
1
TPSC1
0
0
TPSC0
0
R/W Used to divide the source clock (2 × HCAN-2 system
R/W ^clock).
R/W ^{000000: 1 × source clock}
R/W ^{000001: 2 × source clock}
R/W ^{000010: 4 × source clock}
000011: 6 × source clock
:
111110: 124 × source clock
111111: 126 × source clock
15.3.19 Timer Status Register (TSR)
TSR is a 16-bit read-only register that indicates generation of the timer compare match and timer
overflow.
Initial
Bit Bit Name Value R/W Description
15 to 3 —
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
2
TSR2
0
R
Compare Match Flag 1
Indicates that a compare-match condition occurred in
compare match register 1 (TCMR1). When the value set
in TCMR1 matches the timer value (TCMR1 = TCNTR),
this bit is set.
Note: This bit is not set if the TCMR1 value is H'0000.
Also, this bit is read-only and is cleared when
IRR15 (timer compare match interrupt 1) is
cleared.
0: Timer compare match has not occurred
1: Timer compare match has occurred (TCMR1)
[Clearing condition]
• Writing 1 to IRR15
[Setting condition]
• TCMR1 = TCNTR
Rev. 2.00, 09/04, page 457 of 720