HD64F7047F50 Datasheet, PDF (229/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

10.3.9 Timer Synchro Register (TSYR)
TSYR is an 8-bit readable/writable register that selects independent operation or synchronous
operation for the channel 0 to 4 TCNT counters. A channel performs synchronous operation when
the corresponding bit in TSYR is set to 1.
Initial
Bit Bit Name value R/W Description
7
SYNC4 0
R/W Timer Synchro 4 and 3
6
SYNC3 0
R/W These bits are used to select whether operation is
independent of or synchronized with other channels.
When synchronous operation is selected, the TCNT
synchronous presetting of multiple channels, and
synchronous clearing by counter clearing on another
channel, are possible.
To set synchronous operation, the SYNC bits for at least
two channels must be set to 1. To set synchronous clearing,
in addition to the SYNC bit, the TCNT clearing source must
also be set by means of bits CCLR0 to CCLR2 in TCR.
0: TCNT_4 and TCNT_3 operate independently (TCNT
presetting/clearing is unrelated to other channels)
1: TCNT_4 and TCNT_3 performs synchronous operation
TCNT synchronous presetting/synchronous clearing is
possible
5 to 3 
All 0 R
Reserved
These bits are always read as 0. Only 0 should be written to
these bits.
2
SYNC2 0
R/W Timer Synchro 2 to 0
1
SYNC1 0
0
SYNC0 0
R/W These bits are used to select whether operation is
R/W ^{independent of or synchronized with other channels.}
When synchronous operation is selected, the TCNT
synchronous presetting of multiple channels, and
synchronous clearing by counter clearing on another
channel, are possible.
To set synchronous operation, the SYNC bits for at least
two channels must be set to 1. To set synchronous clearing,
in addition to the SYNC bit, the TCNT clearing source must
also be set by means of bits CCLR0 to CCLR2 in TCR.
0: TCNT_2 to TCNT_0 operates independently (TCNT
presetting /clearing is unrelated to other channels)
1: TCNT_2 to TCNT_0 performs synchronous operation
TCNT synchronous presetting/synchronous clearing is
possible
Rev. 2.00, 09/04, page 187 of 720