HD64F7047F50 Datasheet, PDF (362/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Initial
Bit Bit Name Value
R/W
Description
6
WT/IT
0
R/W
Timer Mode Select
Selects whether the WDT is used as a watchdog
timer or interval timer. When TCNT overflows, the
WDT either generates an interval timer interrupt (ITI)
or generates a WDTOVF signal, depending on the
mode selected.
0: Interval timer mode
Interval timer interrupt (ITI) request to the CPU
when TCNT overflows
1: Watchdog timer mode
WDTOVF signal output externally when TCNT
overflows*².
5
TME
0
R/W
Timer Enable
Enables or disables the timer.
0: Timer disabled
TCNT is initialized to H'00 and count-up stops
1: Timer enabled
TCNT starts counting. A WDTOVF signal or
interrupt is generated when TCNT overflows.
4, 3 
All 1
R
Reserved
This bit is always read as 1, and should only be
written with 1.
2
CKS2
0
R/W
Clock Select 2 to 0
1
CKS1
0
0
CKS0
0
R/W
Select one of eight internal clock sources for input to
R/W
TCNT. The clock signals are obtained by dividing the
frequency of the system clock (φ). The overflow
frequency for φ = 40 MHz is enclosed in
parentheses*³.
000: Clock φ/2 (period: 12.8 µs)
001: Clock φ/64 (period: 409.6 µs)
010: Clock φ/128 (period: 0.8 ms)
011: Clock φ/256 (period: 1.6 ms)
100: Clock φ/512 (period: 3.3 ms)
101: Clock φ/1024 (period: 6.6 ms)
110: Clock φ/4096 (period: 26.2 ms)
111: Clock φ/8192 (period: 52.4 ms)
Notes: 1. Only a 0 can be written after reading 1.
2. Section 11.3.3, Reset Control/Status Register (RSTCSR), describes in detail what
happens when TCNT overflows in watchdog timer mode.
3. The overflow interval listed is the time from when the TCNT begins counting at H'00
until an overflow occurs.
Rev. 2.00, 09/04, page 320 of 720