HD64F7047F50 Datasheet, PDF (378/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Initial
Bit Bit Name Value
3
MPIE
0
2
TEIE
0
1
CKE1
0
0
CKE0
0
R/W Description
R/W Multiprocessor Interrupt Enable (enabled only when
the MP bit in SMR is 1 in asynchronous mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of the
RDRF, FER, and ORER status flags in SSR is
prohibited. On receiving data in which the
multiprocessor bit is 1, this bit is automatically cleared
and normal reception is resumed. For details, refer to
section 12.5, Multiprocessor Communication Function.
R/W Transmit End Interrupt Enable
This bit is set to 1, TEI interrupt request is enabled.
R/W Clock Enable 1 and 0
R/W Selects the clock source and SCK pin function.
Asynchronous mode:
00: Internal clock, SCK pin used for input pin (input
signal is ignored) or output pin (output level is
undefined)
01: Internal clock, SCK pin used for clock output (The
output clock frequency is the same as the bit rate)
10: External clock, SCK pin used for clock input (The
input clock frequency is 16 times the bit rate)
11: External clock, SCK pin used for clock input (The
input clock frequency is 16 times the bit rate)
Clocked synchronous mode:
00: Internal clock, SCK pin used for synchronous clock
output
01: Internal clock, SCK pin used for synchronous clock
output
10: External clock, SCK pin used for synchronous
clock input
11: External clock, SCK pin used for synchronous
clock input
Rev. 2.00, 09/04, page 336 of 720