HD64F7047F50 Datasheet, PDF (250/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

2. PWM mode 2
PWM output is generated using one TGR as the cycle register and the others as duty registers.
The output specified in TIOR is performed by means of compare matches. Upon counter
clearing by a synchronization register compare match, the output value of each pin is the initial
value set in TIOR. If the set values of the cycle and duty registers are identical, the output
value does not change when a compare match occurs.
In PWM mode 2, a maximum 8-phase PWM output is possible in combination use with
synchronous operation.
The correspondence between PWM output pins and registers is shown in table 10.31.
Table 10.31 PWM Output Registers and Output Pins
Output Pins
Channel
Registers
PWM Mode 1
PWM Mode 2
0
TGRA_0
TIOC0A
TIOC0A
TGRB_0
TIOC0B
TGRC_0
TIOC0C
TIOC0C
TGRD_0
TIOC0D
1
TGRA_1
TIOC1A
TIOC1A
TGRB_1
TIOC1B
2
TGRA_2
TIOC2A
TIOC2A
TGRB_2
TIOC2B
3
TGRA_3
TIOC3A
Cannot be set
TGRB_3
Cannot be set
TGRC_3
TIOC3C
Cannot be set
TGRD_3
Cannot be set
4
TGRA_4
TIOC4A
Cannot be set
TGRB_4
Cannot be set
TGRC_4
TIOC4C
Cannot be set
TGRD_4
Cannot be set
Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set.
Rev. 2.00, 09/04, page 208 of 720