HD64F7047F50 Datasheet, PDF (748/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Item
Figure 10.34
Complementary PWM
Mode Counter Operation
Page
227
Revisions (See Manual for Details)
Counter value
TGRA_3
TCDR
TCNT_3
Figure 10.73 Contention 261
between TGR Write and
Compare Match
TDDR
H'0000
Pφ
TCNT_4 _TCNTS
TGR write cycle
T1
T2
Address
TGR address
Write signal
Compare
match signal
Figure 10.83 Contention 271
between Overflow and
Counter Clearing
Pφ
TCNT input
clock
Counter clear
signal
TGF
TCFV
Disabled
Figure 10.84 Contention 272
between TCNT Write and
Overflow
Pφ
TCNT write cycle
T1
T2
10.9.5 Usage Notes
TCFV flag
315 1. To set the POE pin as a level-detective pin, a high level
signal must be firstly input to the POE pin.
2. To clear bits POE0F, POE1F, POE2F, POE3F, and OSF to
0, read registers ICSR1 and OCSR. Clear bits, which are
read as 1, to 0, and write 1 to the other bits in the registers.
Rev. 2.00, 09/04, page 706 of 720