HD64F7047F50 Datasheet, PDF (551/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

POE6
POE5
POE4
ICSR2
Input level detection circuit
Falling edge
detection circuit
Low level
detection circuit
High impedance request
control signal
Interrupt request
(MMTPOE)
Pφ/8 Pφ/16 Pφ/128
Figure 16.18 Block Diagram of POE
16.8.2 Input/Output Pins
Table16.5 shows the pin configuration of the POE circuit.
Table 16.5 Pin Configuration
Name
Abbreviation I/O
Port output enable input pins POE4 to POE6 Input
Function
Input request signals for placing
MMT's output pins in high-impedance
state
16.8.3 Register Descriptions
The POE circuit has the following registers.
• Input level control/status register (ICSR2)
Input Level Control/Status Register (ICSR2): The input level control/status register (ICSR2) is
a 16-bit readable/writable register that selects the input mode for pins POE4 to POE6, controls
enabling or disabling of interrupts, and holds status information.
Rev. 2.00, 09/04, page 509 of 720