HD64F7047F50 Datasheet, PDF (440/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

14.2 Register Descriptions
The CMT has the following registers for each channel. For details on register addresses and
register states during each processing, refer to appendix A, Internal I/O Register.
• Compare Match Timer Start Register (CMSTR)
• Compare Match Timer Control/Status Register_0 (CMCSR_0)
• Compare Match Timer Counter_0 (CMCNT_0)
• Compare Match Timer Constant Register_0 (CMCOR_0)
• Compare Match Timer Control/Status Register_1 (CMCSR_1)
• Compare Match Timer Counter_1 (CMCNT_1)
• Compare Match Timer Constant Register_1 (CMCOR_1)
14.2.1 Compare Match Timer Start Register (CMSTR)
The compare match timer start register (CMSTR) is a 16-bit register that selects whether to
operate or halt the channel 0 and channel 1 counters (CMCNT).
Initial
Bit Bit Name Value R/W Description
15 to 2 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
1
STR1
0
R/W Count Start 1
This bit selects whether to operate or halt compare match
timer counter_1.
0: CMCNT_1 count operation halted
1: CMCNT_1 count operation
0
STR0
0
R/W Count Start 0
This bit selects whether to operate or halt compare match
timer counter_0.
0: CMCNT_0 count operation halted
1: CMCNT_0 count operation
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