HD64F7047F50 Datasheet, PDF (475/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

• TXCR0
Bit Bit Name
15 TXCR15
14 TXCR14
13 TXCR13
12 TXCR12
11 TXCR11
10 TXCR10
9
TXCR9
8
TXCR8
7
TXCR7
6
TXCR6
5
TXCR5
4
TXCR4
3
TXCR3
2
TXCR2
1
TXCR1
0

Initial Value R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
Description
Cancel the transmit wait message in the
corresponding mailboxes from 1 to 15. When TXCRn
(n = 1 to 15) is set to 1, the transmit wait message in
mailbox n is canceled.
[Clearing condition]
• Completion of TXPR clearing (when transmit
message is canceled normally), or normal end
process is carried out (when transmit message is
being transmitted, thereby unable to be canceled)
Bit 0 is reserved. This bit is always read as 0. The
write value should always be 0.
To clear the corresponding bit in TXPR, 1 must be
written to the corresponding bit TXCR. When
cancellation has succeeded, the HCAN2 clears the
corresponding TXPR/TXCR bits, and sets the
corresponding ABACK bit. However, once a mailbox
has started transmission, it cannot be canceled by
this bit.
Note: 1 can be written only when the mailbox is
configured as a transmit mailbox.
Rev. 2.00, 09/04, page 433 of 720