HD64F7047F50 Datasheet, PDF (379/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

12.3.7 Serial Status Register (SSR)
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot
be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared.
Initial
Bit Bit Name Value
7
TDRE
1
6
RDRF
0
R/W
R/(W)*
R/(W)*
Description
Transmit Data Register Empty
Displays whether TDR contains transmit data.
[Setting conditions]
• Power-on reset, hardware standby mode, or
software standby mode
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and
data can be written to TDR
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt
request and transferred data to TDR
Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
• When serial reception ends normally and receive
data is transferred from RSR to RDR
[Clearing conditions]
• Power-on reset, hardware standby mode, or
software standby mode
• When 0 is written to RDRF after reading RDRF = 1
• When the DTC is activated by an RXI interrupt and
transferred data from RDR
The RDRF flag is not affected and retains their
previous values when the RE bit in SCR is cleared to
0.
Rev. 2.00, 09/04, page 337 of 720