HD64F7047F50 Datasheet, PDF (547/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Pφ
Address
Status flag
DTC
read cycle
T1 T2
DTC
write cycle
T1 T2
Source address Destination address
Interrupt
request signal
Figure 16.14 Timing of Status Flag Clearing by DTC Controller
16.7 Usage Notes
16.7.1 Module Standby Mode Setting
MMT operation can be disabled or enabled using the module standby control register. The initial
setting is for MMT operation to be halted. Register access is enabled by clearing module standby
mode. For details, refer to section 24, Power-Down Modes.
16.7.2 Notes for MMT Operation
Note that the kinds of operation and contention described below occur during MMT operation.
Contention between Buffer Register Write and Compare Match: If a compare match occurs in
the T2 state of a buffer register (TBRU to TBRW, or TPBR) write cycle, data is transferred from
the buffer register to the compare register (TGR or TPDR) by a buffer operation. The data
transferred is the buffer register write data.
Figure 16.15 shows the timing in this case.
Rev. 2.00, 09/04, page 505 of 720