HD64F7047F50 Datasheet, PDF (441/766 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

14.2.2 Compare Match Timer Control/Status Register_0 and 1(CMCSR_0, CMCSR_1)
The compare match timer control/status register (CMCSR) is a 16-bit register that indicates the
occurrence of compare matches, sets the enable/disable status of interrupts, and establishes the
clock used for incrementation.
Initial
Bit Bit Name Value R/W Description
15 to 8 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
7
CMF
0
R/(W)* Compare Match Flag
This flag indicates whether or not the CMCNT and
CMCOR values have matched.
0: CMCNT and CMCOR values have not matched
1: CMCNT and CMCOR values have matched
[Clearing conditions]
• Write 0 to CMF after reading 1 from it
• When the DTC is activated by an CMI interrupt and
data is transferred with the DISEL bit in DTMR of
DTC = 0
6
CMIE
0
R/W Compare Match Interrupt Enable
This bit selects whether to enable or disable a compare
match interrupt (CMI) when the CMCNT and CMCOR
values have matched (CMF = 1).
0: Compare match interrupt (CMI) disabled
1: Compare match interrupt (CMI) enabled
5 to 2 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
1
CKS1
0
0
CKS0
0
R/W These bits select the clock input to CMCNT among the
R/W
four internal clocks obtained by dividing the peripheral
clock (Pφ). When the STR bit of CMSTR is set to 1,
CMCNT begins incrementing with the clock selected by
CKS1 and CKS0.
00: Pφ/8
01: Pφ/32
10: Pφ/128
11: Pφ/512
Note: * Only 0 can be written, for flag clearing.
Rev. 2.00, 09/04, page 399 of 720