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| PIC18F26K80-I Datasheet, PDF (91/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN™ and nanoWatt XLP Technology | |||
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PIC18F66K80 FAMILY
TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on
Reset,
Brown-out
Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via
WDT
or Interrupt
CCPTMRS
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---0 0000
---x xxxx
---u uuuu
TRISG
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---1 1111
---1 1111
---u uuuu
TRISF
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1111 1111
1111 1111
uuuu uuuu
TRISE
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1111 -111
1111 -111
uuuu -uuu
TRISD
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1111 1111
1111 1111
uuuu uuuu
TRISC
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1111 1111
1111 1111
uuuu uuuu
TRISB
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1111 1111
1111 1111
uuuu uuuu
TRISA(5)
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 111- 1111(5) 111- 1111(5) uuu- uuuu(5)
ODCON
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000
0000 0000
uuuu uuuu
SLRCON
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 -000 0000
-111 1111
-111 1111
LATG
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---x xxxx
---x xxxx
---u uuuu
LATF
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx
xxxx -xxx
uuuu -uuu
LATE
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx -xxx
xxxx xxxx
uuuu uuuu
LATD
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx
xxxx xxxx
uuuu uuuu
LATC
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx
xxxx xxxx
uuuu uuuu
LATB
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx
xxxx xxxx
uuuu uuuu
LATA(5)
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- xxxx(5) xxx- xxxx(5) uuu- uuuu(5)
T4CON
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 -000 0000
-000 0000
-uuu uuuu
TMR4
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000
0000 0000
uuuu uuuu
PORTG
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---x xxxx
---x xxxx
---u uuuu
PORTF
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx
xxxx xxxx
uuuu uuuu
PORTE
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx
xxxx xxxx
uuuu uuuu
PORTD
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx
xxxx xxxx
uuuu uuuu
PORTC
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx
xxxx xxxx
uuuu uuuu
PORTB
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx
xxxx xxxx
uuuu uuuu
PORTA(5)
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- xxxx(5) xxx- xxxx(5) uuu- uuuu(5)
EECON1
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xx-0 x000
uu-0 u000
uu-u uuuu
EECON2
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000
0000 0000
uuuu uuuu
SPBRGH1
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000
0000 0000
uuuu uuuu
SPBRGH2
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000
0000 0000
uuuu uuuu
SPBRG2
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000
0000 0000
uuuu uuuu
RCREG2
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000
0000 0000
uuuu uuuu
TXREG2
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000
0000 0000
uuuu uuuu
IPR5
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1111 1111
1111 1111
uuuu uuuu
PIR5
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000
0000 0000
uuuu uuuu
Legend:
Note 1:
2:
3:
4:
5:
u = unchanged; x = unknown; - = unimplemented bit, read as â0â; q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
See Table 5-3 for Reset value for specific conditions.
Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read as â0â.
ï£ 2010-2012 Microchip Technology Inc.
DS39977F-page 91
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